To achieve greater gains in processing power while lowering power requirements and costs, processor manufacturers have begun moving away from single core processors toward multicore processors. Processors with 2, 4, 8, and more cores have been realized. Performance gains will continue to come from even greater increases in the number of processor cores per chip.
As a result, the architecture of multicore processors has begun to mimic that of multiprocessor devices, leading to a significant bottleneck, namely the intrachip, global communications infrastructure. The challenge is to increase power efficiency while satisfying the substantial bandwidth capacities and stringent latency requirements for on-chip communications when interconnecting a large number of processing cores.
Recent research has focused on intrachip, global communication using electrical, packet-switched micro-networks. These networks-on-chip (NoC) represent a shared medium that is scalable and can provide enough bandwidth to replace many traditional bus-based and/or point-to-point links. However, with a fixed upper limit to the total chip power dissipation, and the communications infrastructure emerging as a major power consuming bottleneck, performance-per-watt is becoming an important design metric for the scaling of NoCs and core multi-processors (CMPs). Accordingly, a need exists for a low-powered, on-chip data communications infrastructure.